Publicação
LP805X : a customizable and low power 8051 soft core for FPGA applications
| Resumo: | In today's advanced technological age, embedded and real time systems have become ubiquitous, covering a wide range of applicability. As a result there is an ever growing need for low power capabilities along with reasonable performance, thus presenting a virtual demand for power-aware devices. The purpose of this work was leveraging key techniques and technologies such as design laziness, componentware design, generative design, separation of mechanism and policy, voltage-frequency island, state encoding, clock gating, and operand isolation, and then investigating their effects while designing an energy and power-conscious microcontroller based on 8051 ISA (Instruction Set Architecture) without disregard to silicon area, required application functionalities and performance. Simulations show that our purposed 2 stage pipeline system with built-in hybrid scheduler operates at 230μW@1MHz. |
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| Autores principais: | Castro, Tiago |
| Outros Autores: | Pinto, Sandro; Silva, Vítor; Lopes, Sérgio F.; Cabral, Jorge; Tavares, Adriano; Yoowattana, S.; Sritriratanarak, W.; Ekpanyapong, M. |
| Assunto: | Processor design Power-aware Design laziness Componentware Generative design Voltage-frequency island Power and clock gating |
| Ano: | 2013 |
| País: | Portugal |
| Tipo de documento: | comunicação em conferência |
| Tipo de acesso: | acesso restrito |
| Instituição associada: | Universidade do Minho |
| Idioma: | inglês |
| Origem: | RepositóriUM - Universidade do Minho |
| Resumo: | In today's advanced technological age, embedded and real time systems have become ubiquitous, covering a wide range of applicability. As a result there is an ever growing need for low power capabilities along with reasonable performance, thus presenting a virtual demand for power-aware devices. The purpose of this work was leveraging key techniques and technologies such as design laziness, componentware design, generative design, separation of mechanism and policy, voltage-frequency island, state encoding, clock gating, and operand isolation, and then investigating their effects while designing an energy and power-conscious microcontroller based on 8051 ISA (Instruction Set Architecture) without disregard to silicon area, required application functionalities and performance. Simulations show that our purposed 2 stage pipeline system with built-in hybrid scheduler operates at 230μW@1MHz. |
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