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Integrated 5.7 GHz chip-size antenna for wireless sensor networks

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Bibliographic Details
Summary:We report on design, fabrication and characterization of chip-size antennas for operation at 5.7 GHz and use in wireless sensor networks. Application of wafer-level chipscale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna types (patch and folded patch) allows on-chip integration and is the main novelty of our work. A short-range wireless link between two systems both equipped with an 8x8 mm2 patch antenna (measured characteristics: 5.705 GHz central frequency, 90 MHz bandwidth @ -10 dB, 0.3 dB gain, 18% efficiency) realized on a high-resistivity silicon (HRS) substrate is demonstrated. A folded-patch antenna built on two stacked glass substrates allows size reduction down to 4.5x4x1 mm3 and has a projected efficiency of 60%.
Main Authors:Mendes, P. M.
Other Authors:Polyakov, A.; Bartek, M.; Burghartz, J. N.; Correia, J. H.
Subject:Integrated antenna Wireless sensor networks Wafer level packaging Antenna measurements Bandwidth Chip scale packaging Fabrication Frequency measurement Gain measurement Patch antennas Wafer bonding Wafer scale integration
Year:2003
Country:Portugal
Document type:conference paper
Access type:open access
Associated institution:Universidade do Minho
Language:English
Origin:RepositóriUM - Universidade do Minho
Description
Summary:We report on design, fabrication and characterization of chip-size antennas for operation at 5.7 GHz and use in wireless sensor networks. Application of wafer-level chipscale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna types (patch and folded patch) allows on-chip integration and is the main novelty of our work. A short-range wireless link between two systems both equipped with an 8x8 mm2 patch antenna (measured characteristics: 5.705 GHz central frequency, 90 MHz bandwidth @ -10 dB, 0.3 dB gain, 18% efficiency) realized on a high-resistivity silicon (HRS) substrate is demonstrated. A folded-patch antenna built on two stacked glass substrates allows size reduction down to 4.5x4x1 mm3 and has a projected efficiency of 60%.

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