Publicação

MCU-wide timing side channels and their detection

Detalhes bibliográficos
Resumo:	Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism between attacker and victim task execution. However, contradicting common intuitions, recent activities demonstrate that this threat is real even in microcontroller SoCs without such features. In this paper, we describe SoC-wide timing side channels previously neglected by security analysis and present a new formal method to close this gap. In a case study on the RISC-V Pulpissimo SoC, our method detected a vulnerability to a previously unknown attack variant that allows an attacker to obtain information about a victim's memory access behavior. After implementing a conservative fix, we were able to verify that the SoC is now secure w.r.t. the considered class of timing side channels.
Autores principais:	Müller, Johannes
Outros Autores:	Antón, Anna Lena Duque; Deutschmann, Lucas; Mehmedagic, Dino; Rodrigues, Cristiano; Oliveira, Daniel José Cunha; Fadiheh, Mohammad Rahmani; Devarajegowda, Keerthikumara; Pinto, Sandro; Stoffel, Dominik; Kunz, Wolfgang
Assunto:	Formal Verification Hardware Security Timing Side Channels
Ano:	2024
País:	Portugal
Tipo de documento:	comunicação em conferência
Tipo de acesso:	acesso aberto
Instituição associada:	Universidade do Minho
Idioma:	inglês
Origem:	RepositóriUM - Universidade do Minho

Descrição
Resumo:	Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism between attacker and victim task execution. However, contradicting common intuitions, recent activities demonstrate that this threat is real even in microcontroller SoCs without such features. In this paper, we describe SoC-wide timing side channels previously neglected by security analysis and present a new formal method to close this gap. In a case study on the RISC-V Pulpissimo SoC, our method detected a vulnerability to a previously unknown attack variant that allows an attacker to obtain information about a victim's memory access behavior. After implementing a conservative fix, we were able to verify that the SoC is now secure w.r.t. the considered class of timing side channels.

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