Publicação
Decimal addition on FPGA based on a mixed BCD/excess-6 representation
| Resumo: | Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition. |
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| Autores principais: | Neto, Horácio |
| Outros Autores: | Véstias, Mário |
| Assunto: | Decimal addition Parallel addition Binary/decimal addition Multioperand addition Excess-6 coding FPGA |
| Ano: | 2017 |
| País: | Portugal |
| Tipo de documento: | artigo |
| Tipo de acesso: | acesso restrito |
| Instituição associada: | Universidade Politécnica de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Científico da Universidade Politécnica de Lisboa |
| Resumo: | Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition. |
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