Publicação
Improving the area of fast parallel decimal multipliers
| Resumo: | Financial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation. |
|---|---|
| Autores principais: | Véstias, Mário |
| Outros Autores: | Cláudio de Campos Neto, Horácio |
| Assunto: | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| Ano: | 2018 |
| País: | Portugal |
| Tipo de documento: | artigo |
| Tipo de acesso: | acesso aberto |
| Instituição associada: | Universidade Politécnica de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Científico da Universidade Politécnica de Lisboa |
| _version_ | 1880398296960204800 |
|---|---|
| author | Véstias, Mário |
| author2 | Cláudio de Campos Neto, Horácio |
| author2_role | author |
| author_facet | Véstias, Mário Cláudio de Campos Neto, Horácio |
| author_role | author |
| contributor_name_str_mv | RCIPL |
| country_str | PT |
| creators_json_txt | [{\"Person.name\":\"Véstias, Mário\",\"Person.identifier.cienciaID\":\"4717-C2C7-3F2C\",\"Person.identifier.orcid\":\"0000-0001-8556-4507\",\"Person.identifier.researcherID\":\"H-9953-2012\",\"Person.identifier.scopusAuthorID\":\"14525867300\"},{\"Person.name\":\"Cláudio de Campos Neto, Horácio\",\"Person.identifier.cienciaID\":\"9915-3BDF-5C35\",\"Person.identifier.orcid\":\"0000-0002-3621-8322\"}] |
| datacite.contributors.contributor.contributorName.fl_str_mv | RCIPL |
| datacite.creators.creator.creatorName.fl_str_mv | Véstias, Mário Cláudio de Campos Neto, Horácio |
| datacite.date.Accepted.fl_str_mv | 2018-05-22T00:00:00Z |
| datacite.date.available.fl_str_mv | 2018-06-06T10:11:35Z |
| datacite.date.embargoed.fl_str_mv | 2018-06-06T10:11:35Z |
| datacite.rights.fl_str_mv | http://purl.org/coar/access_right/c_abf2 |
| datacite.subjects.subject.fl_str_mv | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| datacite.titles.title.fl_str_mv | Improving the area of fast parallel decimal multipliers |
| dc.contributor.none.fl_str_mv | RCIPL |
| dc.creator.none.fl_str_mv | Véstias, Mário Cláudio de Campos Neto, Horácio |
| dc.date.Accepted.fl_str_mv | 2018-05-22T00:00:00Z |
| dc.date.available.fl_str_mv | 2018-06-06T10:11:35Z |
| dc.date.embargoed.fl_str_mv | 2018-06-06T10:11:35Z |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | http://hdl.handle.net/10400.21/8571 |
| dc.language.none.fl_str_mv | eng |
| dc.publisher.none.fl_str_mv | Elsevier |
| dc.rights.none.fl_str_mv | http://purl.org/coar/access_right/c_abf2 |
| dc.subject.none.fl_str_mv | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| dc.title.fl_str_mv | Improving the area of fast parallel decimal multipliers |
| dc.type.none.fl_str_mv | http://purl.org/coar/resource_type/c_6501 |
| description | Financial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation. |
| dirty | 0 |
| eu_rights_str_mv | openAccess |
| format | article |
| fulltext.url.fl_str_mv | https://repositorio.ipl.pt/bitstreams/16d00f98-8bd8-43b6-95d3-de4eb14ad808/download |
| id | ripl_34c24b4526156737726ffdd8b4465f96 |
| identifier.url.fl_str_mv | http://hdl.handle.net/10400.21/8571 |
| inst_facet_str | urn:organizationAcronym:ipl{{{_:::_}}}Universidade Politécnica de Lisboa |
| instacron_str | ipl |
| institution | Universidade Politécnica de Lisboa |
| instname_str | Universidade Politécnica de Lisboa |
| language | eng |
| network_acronym_str | ripl |
| network_name_str | Repositório Científico da Universidade Politécnica de Lisboa |
| oai_identifier_str | oai:repositorio.ipl.pt:10400.21/8571 |
| organization_str_mv | urn:organizationAcronym:ipl |
| person_str_mv | Véstias, Mário Véstias, Mário https://www.ciencia-id.pt/4717-C2C7-3F2C 4717-C2C7-3F2C http://orcid.org/0000-0001-8556-4507 0000-0001-8556-4507 Cláudio de Campos Neto, Horácio Cláudio de Campos Neto, Horácio https://www.ciencia-id.pt/9915-3BDF-5C35 9915-3BDF-5C35 http://orcid.org/0000-0002-3621-8322 0000-0002-3621-8322 |
| publishDate | 2018 |
| publisher.none.fl_str_mv | Elsevier |
| repo_facet_str | urn:repositoryAcronym:ripl{{{_:::_}}}Repositório Científico da Universidade Politécnica de Lisboa |
| reponame_str | Repositório Científico da Universidade Politécnica de Lisboa |
| repository_id_str | urn:repositoryAcronym:ripl |
| service_str_mv | urn:repositoryAcronym:ripl |
| spelling | engElsevierpt_PTFinancial and commercial applications depend on decimal arithmetic because they must produce results that match exactly those obtained by human calculations. Decimal multiplication is a frequently used operation in these applications and also in the design of decimal floating-point units. In this paper we propose a new architecture for parallel decimal multiplication that improves the area of previous decimal multipliers while keeping the best performances. A decimal adder [1] based on a mixed BCD/excess-6 representation of the operands is utilized. A new partial product generation unit is proposed based on a 5221 recoding of the multiplier digits. With the proposed multiplier, we are able to improve on state-of-the-art parallel decimal multipliers targeting LUT-6 FPGAs. Compared to previous decimal multipliers, implementation results for 2, 4, 8, 16, 32 and 34-digits show that the proposed multiplier achieves over 20% better area without performance degradation.application/pdfpt_PTImproving the area of fast parallel decimal multipliersPersonalVéstias, MárioDSpacehttp://dspace.org/items/a7d22b29-c961-45ac-bc09-cd5e1002f1e8DSpacehttp://dspace.org/items/a7d22b29-c961-45ac-bc09-cd5e1002f1e8VéstiasMárioCiência IDhttps://www.ciencia-id.pt4717-C2C7-3F2CORCIDhttp://orcid.org0000-0001-8556-4507Researcher IDhttps://www.researcherid.comH-9953-2012Scopus Author IDhttps://www.scopus.com14525867300PersonalCláudio de Campos Neto, HorácioDSpacehttp://dspace.org/items/38334d5e-83e8-494c-a9e0-396299376d97DSpacehttp://dspace.org/items/38334d5e-83e8-494c-a9e0-396299376d97Cláudio de Campos NetoHorácioCiência IDhttps://www.ciencia-id.pt9915-3BDF-5C35ORCIDhttp://orcid.org0000-0002-3621-8322HostingInstitutionOrganizationalRCIPLe-mailmailto:rcaap@sp.ipl.ptrcaap@sp.ipl.ptISSNIsPartOf0141-9331DOIIsPartOf10.1016/j.micpro.2018.05.0152018-06-06T10:11:35Z2018-05-222018-05-22T00:00:00ZHandlehttp://hdl.handle.net/10400.21/8571http://purl.org/coar/access_right/c_abf2open accessDecimal multiplicationParallel multiplicationExcess-6 coding5221 codingFPGA1242747 bytesliteraturehttp://purl.org/coar/resource_type/c_6501journal articlehttp://purl.org/coar/access_right/c_abf2application/pdffulltexthttps://repositorio.ipl.pt/bitstreams/16d00f98-8bd8-43b6-95d3-de4eb14ad808/downloadMicroprocessors and Microsystems6196107 |
| spellingShingle | Improving the area of fast parallel decimal multipliers Véstias, Mário Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| status | SINGLETON |
| subject.fl_str_mv | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| title | Improving the area of fast parallel decimal multipliers |
| title_full | Improving the area of fast parallel decimal multipliers |
| title_fullStr | Improving the area of fast parallel decimal multipliers |
| title_full_unstemmed | Improving the area of fast parallel decimal multipliers |
| title_short | Improving the area of fast parallel decimal multipliers |
| title_sort | Improving the area of fast parallel decimal multipliers |
| topic | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| topic_facet | Decimal multiplication Parallel multiplication Excess-6 coding 5221 coding FPGA |
| url | http://hdl.handle.net/10400.21/8571 |
| visible | 1 |
Atividades financiadas
Não foram encontrados projetos financiados.