Publicação
Trends Of CPU, GPU and FPGA for high-performance computing
| Resumo: | Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM). |
|---|---|
| Autores principais: | Véstias, Mário |
| Outros Autores: | Neto, Horácio |
| Assunto: | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| Ano: | 2014 |
| País: | Portugal |
| Tipo de documento: | documento de conferência |
| Tipo de acesso: | acesso restrito |
| Instituição associada: | Universidade Politécnica de Lisboa |
| Idioma: | inglês |
| Origem: | Repositório Científico da Universidade Politécnica de Lisboa |
| _version_ | 1880398249506897920 |
|---|---|
| author | Véstias, Mário |
| author2 | Neto, Horácio |
| author2_role | author |
| author_facet | Véstias, Mário Neto, Horácio |
| author_role | author |
| contributor_name_str_mv | RCIPL |
| country_str | PT |
| creators_json_txt | [{\"Person.name\":\"Véstias, Mário\",\"Person.identifier.cienciaID\":\"4717-C2C7-3F2C\",\"Person.identifier.orcid\":\"0000-0001-8556-4507\",\"Person.identifier.researcherID\":\"H-9953-2012\",\"Person.identifier.scopusAuthorID\":\"14525867300\"},{\"Person.name\":\"Neto, Horácio\"}] |
| datacite.contributors.contributor.contributorName.fl_str_mv | RCIPL |
| datacite.creators.creator.creatorName.fl_str_mv | Véstias, Mário Neto, Horácio |
| datacite.date.Accepted.fl_str_mv | 2014-10-01T00:00:00Z |
| datacite.date.available.fl_str_mv | 2015-08-19T09:59:06Z |
| datacite.date.embargoed.fl_str_mv | 2015-08-19T09:59:06Z |
| datacite.rights.fl_str_mv | http://purl.org/coar/access_right/c_16ec |
| datacite.subjects.subject.fl_str_mv | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| datacite.titles.title.fl_str_mv | Trends Of CPU, GPU and FPGA for high-performance computing |
| dc.contributor.none.fl_str_mv | RCIPL |
| dc.creator.none.fl_str_mv | Véstias, Mário Neto, Horácio |
| dc.date.Accepted.fl_str_mv | 2014-10-01T00:00:00Z |
| dc.date.available.fl_str_mv | 2015-08-19T09:59:06Z |
| dc.date.embargoed.fl_str_mv | 2015-08-19T09:59:06Z |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | http://hdl.handle.net/10400.21/4840 |
| dc.language.none.fl_str_mv | eng |
| dc.publisher.none.fl_str_mv | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| dc.rights.none.fl_str_mv | http://purl.org/coar/access_right/c_16ec |
| dc.subject.none.fl_str_mv | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| dc.title.fl_str_mv | Trends Of CPU, GPU and FPGA for high-performance computing |
| dc.type.none.fl_str_mv | http://purl.org/coar/resource_type/c_c94f |
| description | Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM). |
| dirty | 0 |
| eu_rights_str_mv | restrictedAccess |
| format | conferenceObject |
| fulltext.url.fl_str_mv | https://repositorio.ipl.pt/bitstreams/7ecf934d-ade4-4c14-8de1-247186e0601d/download |
| funder_facet_str_mv | FCT{{{_:::_}}}Fundação para a Ciência e a Tecnologia |
| funding.funder.alternateName_str_mv | FCT |
| funding.funder.identifier_str_mv | http://doi.org/10.13039/501100001871 |
| funding.funder.name_str_mv | Fundação para a Ciência e a Tecnologia |
| funding.identifier_str_mv | PEst-OE/EEI/LA0021/2013 |
| funding.name_str_mv | 6817 - DCRRNI ID |
| funding_str_mv | PEst-OE/EEI/LA0021/2013 info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/PEst-OE%2FEEI%2FLA0021%2F2013/PT |
| id | ripl_1b3aa1161baa5d459f4a6eded39ddfb6 |
| identifier.url.fl_str_mv | http://hdl.handle.net/10400.21/4840 |
| inst_facet_str | urn:organizationAcronym:ipl{{{_:::_}}}Universidade Politécnica de Lisboa |
| instacron_str | ipl |
| institution | Universidade Politécnica de Lisboa |
| instname_str | Universidade Politécnica de Lisboa |
| language | eng |
| network_acronym_str | ripl |
| network_name_str | Repositório Científico da Universidade Politécnica de Lisboa |
| oai_identifier_str | oai:repositorio.ipl.pt:10400.21/4840 |
| organization_str_mv | urn:organizationAcronym:ipl |
| person_str_mv | Véstias, Mário Véstias, Mário https://www.ciencia-id.pt/4717-C2C7-3F2C 4717-C2C7-3F2C http://orcid.org/0000-0001-8556-4507 0000-0001-8556-4507 Neto, Horácio |
| publishDate | 2014 |
| publisher.none.fl_str_mv | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| repo_facet_str | urn:repositoryAcronym:ripl{{{_:::_}}}Repositório Científico da Universidade Politécnica de Lisboa |
| reponame_str | Repositório Científico da Universidade Politécnica de Lisboa |
| repository_id_str | urn:repositoryAcronym:ripl |
| service_str_mv | urn:repositoryAcronym:ripl |
| spelling | engIEEE - Institute of Electrical and Electronics Engineers Inc.porFloating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).application/pdfporTrends Of CPU, GPU and FPGA for high-performance computingPersonalVéstias, MárioDSpacehttp://dspace.org/items/a7d22b29-c961-45ac-bc09-cd5e1002f1e8DSpacehttp://dspace.org/items/a7d22b29-c961-45ac-bc09-cd5e1002f1e8VéstiasMárioCiência IDhttps://www.ciencia-id.pt4717-C2C7-3F2CORCIDhttp://orcid.org0000-0001-8556-4507Researcher IDhttps://www.researcherid.comH-9953-2012Scopus Author IDhttps://www.scopus.com14525867300Neto, HorácioHostingInstitutionOrganizationalRCIPLe-mailmailto:rcaap@sp.ipl.ptrcaap@sp.ipl.ptISBNIsPartOf978-300044645-0DOIIsPartOf10.1109/FPL.2014.69274832015-08-19T09:59:06Z2014-102014-10-01T00:00:00ZHandlehttp://hdl.handle.net/10400.21/4840http://purl.org/coar/access_right/c_16ecrestricted accessHigh-Performance ComputingField-Programmable Gate Arrays (FPGA)1321657 bytesFundação para a Ciência e a TecnologiaStrategic Project - LA 21 - 2013-2014info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/PEst-OE%2FEEI%2FLA0021%2F2013/PTPEst-OE/EEI/LA0021/20136817 - DCRRNI IDCrossref Funder IDhttp://doi.org/10.13039/501100001871other research producthttp://purl.org/coar/resource_type/c_c94fconference objecthttp://purl.org/coar/access_right/c_16ecapplication/pdffulltexthttps://repositorio.ipl.pt/bitstreams/7ecf934d-ade4-4c14-8de1-247186e0601d/downloadConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPLNew York |
| spellingShingle | Trends Of CPU, GPU and FPGA for high-performance computing Véstias, Mário High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| status | SINGLETON |
| subject.fl_str_mv | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| title | Trends Of CPU, GPU and FPGA for high-performance computing |
| title_full | Trends Of CPU, GPU and FPGA for high-performance computing |
| title_fullStr | Trends Of CPU, GPU and FPGA for high-performance computing |
| title_full_unstemmed | Trends Of CPU, GPU and FPGA for high-performance computing |
| title_short | Trends Of CPU, GPU and FPGA for high-performance computing |
| title_sort | Trends Of CPU, GPU and FPGA for high-performance computing |
| topic | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| topic_facet | High-Performance Computing Field-Programmable Gate Arrays (FPGA) |
| url | http://hdl.handle.net/10400.21/4840 |
| visible | 1 |