Filters that belong to the class of "Generalized Feedfoward Filters" (GNFF), can he considered as models in-between FIR and IIR according to its complexity, stability and capacity. This dissertation is concerned in particular with issues related with analogue implementation of one of these GNFF, called the gamma filter. (...)

In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.

Resistive switching behaviour has been demonstrated to be a common characteristic to many materials. In this regard, research teams to date have produced a plethora of different devices exhibiting diverse behaviour, but when system design is considered, finding a ‘one-model-fits-all’ solution can be quite difficult, or even impossible. However, it is in the interest of the community to achieve more general modelling tools for design that allows a quick model update as devices evolve. Laying the grounds with such a principle, this paper presents an artificial neural network learning approach to resistive switching modelling. The efficacy of the method is demonstrated firstly with two simulated devices and secondly with a 4 µm2 amorphous IGZO device. For the amorphous IGZO device, a normalized root-mean-squared error (NRMSE) of 5.66 × 10−3 is achieved with a [2, 50, 50, 1] network structure, representing a good balance between model complexity and accuracy. A brief study on the number of hidden layers and neurons and its effect on network performance is also conducted with the best NRMSE reported at 4.63 × 10−3 . The low error rate achieved in both simulated and real-world devices is a good indicator that the presented approach is flexible and can suit multiple device types.

A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal, 0.35 μm CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.

This paper presents a high speed digitally programmable Ring Oscillator (RO) using Indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). Proposed circuit ensures high speed compared to the conventional ROs using negative skewed scheme, in which each inverter delay is reduced by pre-maturely switching on/off the transistors. In addition, by controlling the load capacitance of each inverter through digital control bits, a programmable frequency of oscillation was attained. Proposed RO performance is compared with two conventional designs under same conditions. From simulation, it has been observed that the proposed circuit has shown a higher frequency of oscillations (283 KHz) compared to the conventional designs (76.52 KHz and 144.9 KHz) under same conditions. Due to the programmable feature, the circuit is able to generate 8 different linearly spaced frequencies ranging from 241.2 KHz to 283 KHz depending upon three digital control bits with almost rail-to-rail voltage swing. The circuit is a potential on-chip clock generator in many real-world flexible systems, such as, smart packaging, wearable devices, RFIDs and displays that need multi frequencies.