The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people and processes interact with each other. Challenges in endpoint devices communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This article presents a 6LoWPAN accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous endpoint devices at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing- and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 µJ.

In the near future, autonomous vehicles with full self-driving features will populate our public roads. However, fully autonomous cars will require robust perception systems to safely navigate the environment, which includes cameras, RADAR devices, and Light Detection and Ranging (LiDAR) sensors. LiDAR is currently a key sensor for the future of autonomous driving since it can read the vehicle’s vicinity and provide a real-time 3D visualization of the surroundings through a point cloud representation. These features can assist the autonomous vehicle in several tasks, such as object identification and obstacle avoidance, accurate speed and distance measurements, road navigation, and more. However, it is crucial to detect the ground plane and road limits to safely navigate the environment, which requires extracting information from the point cloud to accurately detect common road boundaries. This article presents a survey of existing methods used to detect and extract ground points from LiDAR point clouds. It summarizes the already extensive literature and proposes a comprehensive taxonomy to help understand the current ground segmentation methods that can be used in automotive LiDAR sensors.

With the increased complexity of low-end devices in the Internet of Things (IoT), mainly due to the connectivity and interoperability requirements, the development and configuration of embedded operating systems (OSes) for such devices is not straight forward. The complexity of the communication requirements is usually mitigated by the OS, e.g., the Contiki-OS, as it already incorporates an IoT-compliant network stack. Yet, the configuration of such stack requires major knowledge on the code structure, leading to additional development time, particularly when the network comprises several wireless nodes and individual configurations with subsequent firmware that needs to be generated. Based on a developed software modeling domain-specific language, this paper presents the EL4IoT framework. It aims to reduce and ease the development time by promoting a design automation tool that can configure, and automatically generate code (ready to compile) for low-end IoT devices running the Contiki-OS. Although leveraging the whole Contiki-OS modeling, this work only refactored and modeled the network stack while approaching the OS itself as one big building block or component. The proposed approach can be extended to other IoT-enabled OSes as well as integrated in other design automation tools.

The purpose of this paper is to propose a mathematical programming approach to minimize the total cost in a biomass supply chain. A company that collects material from forests, transforms it into chipped product, stores and delivers it to its customers is considered. For tackling all the aspects of the supply chain management, a mixed integer programming model that supports tactical and operational decisions was developed and optimized using a general purpose solver. The model was implemented in C++ and several computational tests have been performed.

This article describes a non-intrusive hardware acceleration approach for Dynamic Binary Translation (DBT) in modern resource-constrained embedded systems, detailing its motivation, design decisions and overall architecture. It was deployed and tested on DBTOR, an in-house DBT system that targets constrained embedded systems. The performed evaluations demonstrate the feasibility of the proposed method in handling condition code (CC) flags, peripheral remapping and interrupt support, by running legacy MCS-51 code on a modern Arm v7-M architecture (Cortex-M3) that resorts field-programmable gate array (FPGA) technology for acceleration purposes.

Wireless Sensor Networks (WSNs) have been employed in a wide range of applications due to the low-cost and ease of installation features. One of the applications is in the road safety and highways, in a wide range of scenarios. In this paper, an IoT-based system for collision detection on guardrails is presented. The developed system implements an IoT standard stack in order to provide the connectivity and interoperability of the network devices. Also a theoretical analysis for the energy consumption is presented and simulated. A Markov Chain model is used to observe the energy consumption of the proposed algorithm in each node. An experimental evaluation is also carried out in order to check the theoretical analysis and it was based on the real energy consumption of the developed nodes. At last, a full deployment on a highway of the developed system allowed a full evaluation of the connectivity and performance of the whole system.

CROSSCON is a 3-year, multi-million euro, Research and Innovation Action funded under Horizon Europe. The project aims to design a new open, modular, highly portable, and vendor-independent IoT security stack that can run on various devices using heterogeneous hardware architectures, including RISC-V. The Consortium sees in RISC-V a two-fold opportunity. Firstly, by aiming to develop an interoperable reference security stack, we believe we can contribute to the expected specifications of ongoing initiatives for Trusted Execution and Confidential Computing on Application processors (i.e., CoVE) and microcontrollers. Secondly, RISC-V offers a unique opportunity to develop novel security hardware extensions for software services, either by creating extensions directly to the ISA or developing non-ISA hardware mechanisms that support the efficient implementation of security guarantees at the application level.

The number of Internet of Things (IoT) embedded devices is estimated to reach 30 billion by 2030, leading to a highly dynamic landscape where distinct devices have to coexist. The rapid proliferation of different architectures and platforms requires a unified solution that can be supported by different devices, while providing a wide range of services to cope with the ongoing challenges of connecting devices to the Internet. CROSSCON, a 3-year Research and Innovation Action funded under Horizon Europe, aims to address these challenges by designing a new open, modular, highly portable, and vendor-independent IoT security stack that can run on various devices using heterogeneous embedded hardware architectures, such as ARM and RISC-V. At this stage of development, CROSSCON already specifies a unified level of abstraction, encompassing several components across multiple heterogeneous hardware platforms. It currently supports a bare-metal TEE for constrained devices, and novel security features provided by the CROSSCON hypervisor, such as per-VM TEE and Dynamic VM creation.