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  1. 1

    Integer DCT Approximation With Arbitrary Size and Adjustable Precision

    Publicação
    por Thomaz, Lucas A.
    Outros Autores: Assunção, Pedro A. A.; Tavora, Luis M. N.; Faria, Sérgio M. M. de
    Origem: IC-online
    This letter proposes a method to obtain integer reversible discrete cosine transforms for generic transform-based coding schemes. The novelty of the proposed method, which is based on decomposition of the DCT-II matrix into two triangular and one diagonal matrices, is twofold: (i) the new matrices can be of arbitrary size, i.e., any square N\times N dimension, thus suitable for applications where non power-of-2 dimensions are required; (ii) they can be designed with adjustable precision in a trade-off with the number of representation bits. Furthermore, improvements are also proposed over the base scheme to avoid numerical issues when working with large matrices and to obtain more reliable approximations. The performance evaluation demonstrate the effectiveness of the proposed transforms to approximate the coding gain capabilities of the original DCT-II.
    2020 artigo Portugal acesso aberto
  2. 2

    Transform co-processor for AV1 video coding standard

    Publicação
    por Inocêncio, Miguel Oliveira
    This dissertation presents a study made of the video coding standard AV1. The research provides statistical results referring to various encoding options, such as the most commonly used Transform kernel, vector sizes, the number of bits used in cosine approximations, amongst others. With the gathered results, optimization measures were implemented on the reference encoder, achieving a 3% decrease in the total encoding time, with 81% reduction in the memory used to store cosine coefficients. The algorithm implemented in software was then described in VHDL, obtaining two implementable architectures. The first allows a high degree of parallelization, obtaining all transformed vector sizes within 22 clock cycles, being able to maintain FHD video at 30 frames per second, at an operating frequency of 187 MHz. The second minimizes the amount of logic, although it does not allow the calculation of multiple vector sizes in parallel. This implementation was synthesized and tested on a Nexys 4 board, occupying 79.93% of total FPGA area and 50 mW consumption. On the hardware kit on which it was implemented, this architecture is able to process HD video at 30 frames per second.
    2019 dissertação de mestrado Portugal acesso aberto