Embedded systems have become integral to numerous industries, ranging from automotive and aerospace to consumer electronics and industrial automation. The evolution of these systems, driven by the demand for intelligent, interconnected devices, has resulted in increased complexity, particularly with the integration of Mixed Criticality Systems (MCS). These systems consolidate multiple safety- and time-critical functionalities on a single platform, necessitating robust solutions for resource isolation, performance optimization, and security. Virtualization technology, and specifically the use of hypervisors, has emerged as a key enabler for MCS, providing strong isolation, resource partitioning, and the flexibility to run multiple Operating Systems (OSes) on shared hardware. However, as peripheral devices like Peripheral Component Interconnect Express (PCIe) become more complex and ubiquitous in modern embedded systems, the challenges associated with device virtualization, including interrupt management, configuration space control, and Direct Memory Access (DMA), have grown significantly. PCIe, now the de facto standard for high-performance device communication, introduces unique hurdles due to its serial architecture, mandatory support for in-band Message Signaled Interrupt (MSI), and reliance on hardware components such as the Input-Output Memory Management Unit (IOMMU) for secure memory access. This dissertation focuses on extending PCIe device support in the Bao hypervisor to enable passthrough of PCIe bus to a single guest OS. The proposed solution ensures secure and efficient management of PCIe configuration space, interrupt delivery, and DMA operations, addressing key challenges related to system isolation and performance in MCS. By implementing a lightweight and robust PCIe virtualization mechanism, this work enhances Bao’s capabilities, making it suitable for a broader range of use cases while maintaining strict real-time and security requirements.

Virtualization is a settled technology for embedded systems that allows to consolidate functions while reducing system size, cost, and power. It also enhances security and safety by using isolation and software redundancy. Allied with an emerging core generated from the RISC-V ISA which is already deployed by companies like Nvidia, Google, and Qualcomm, a solution to provide a virtualized, safe and secure environment for an OS to run on top of is a goal of this thesis. Being RISC-V an open-source and royalty-free ISA, the transaction between academic-only to commercial use has been vertiginous. The main goal of this thesis is to implement, from scratch, a machine-mode type-1 hypervisor for a RISC-V core similar to the LTZVisor which is deployed on top of an ARM core, to enable the usage of the processor by different OSs while having the feeling that all of them execute at the same time and provide temporal and spatial isolation. This project is developed using a RISC-V core generated using the Rocket-chip and deployed on a Zybo board. Being V-Visor a lightweight hypervisor developed for the RISC-V architecture, it has features from both full and paravirtualization derived from the constraints introduced by the core itself. It takes advantage of the PMP mechanism to provide spatial isolation for each guest while using a RR scheduling algorithm to implement temporal isolation while having a deterministic behavior.

O rápido crescimento dos veículos aéreos não tripulados (UAV) impõe exigências de criticalidade mista: o controlo de voo (crítico) tem de coexistir com o software não-crítico da missão obedecendo aos limites de tamanho, peso, potência e custo (SWaP-C). As plataformas convencionais, multi-board, adicionam peso e latência nas comunicações e a separação por hardware é insuficiente, devido às interfaces partilhadas. Os esforços de consolidação em curso dependem de hipervisores proprietários ou assentam em implementações que dependem da platforma/aplicação ou que foram abandonados. Outras abordagens focam-se apenas na pilha de software da missão usando contentores ou componentes verificados formalmente. O contentor não garante o isolamento adequado, e ambos focam-se apenas na pilha da missão, deixando as comunicações e o piloto automático desprotegidos. Tais suposições são inseguras dada a extensa superfície de ataque dos UAVs e as vulnerabilidades reportadas nos pilotos automáticos de código aberto e sistemas operativos de tempo real comerciais. No presente trabalho concebemos e avaliamos uma consolidação de pilhas de software criticidade mista em UAVs recorrendo ao Bao, um hipervisor de particionamento estático de tipo I. Implementamos duas pilhas de software numa única plataforma (Raspberry Pi 4 + PilotPi): uma não supervisionada (USPFS), usada como base de comparação, e uma supervisionada (SSPFS), onde o PX4 (piloto automático) e uma aplicação de vídeo em tempo real (missão) executam como guests separados. Para partilhar periféricos com segurança, adicionamos ao Bao um mecanismo de supervisão por mailbox que medeia transações de firmware num barramento partilhado, prevenindo acessos indevidos entre domínios. As experiências demonstram que as falhas injetadas no guest não crítico provocam apenas a falha deste, enquanto o PX4 mantém o controlo e a UAV em voo. A avaliação realizada com o MiBench e nos testes de aplicação, indicam penalizações reduzidas no desempenho: 2% no escalonamento de tarefas do PX4 e na captura de vídeo. Os testes de voo demonstraram a robustez do controlo de posição e um aumento reduzido na carga do CPU (6%). O particionamento estático promove o isolamento entre domínios e o cache coloring mitiga a interferência entre eles. Em suma, um hipervisor de particionamento estático, como o Bao, permite consolidar as pilhas de software de voo e de missão numa única plataforma com impacto reduzido no desempenho, viabilizando sistemas confiáveis de criticidade mista em UAVs de código aberto.

This dissertation investigates the modernization of a corporate virtualization estate whose Nuxis-based platform has reached end-of-life. A risk-driven evaluation framework is defined to compare technical, operational, and economic options, supported by a state-of-the-art synthesis of hypervisors and management stacks. Requirements and acceptance criteria are made explicit to guide decision-making across availability, disaster recovery, security/governance, observability, automation, and cost (TCO/ROI). A controlled proof-of-concept (PoC) validates key platform behaviors on a single representative virtual machine, exercising live migration, backup/restore, remote backup replication, centralized log forwarding, and API/RBAC enforcement. The results indicate feasibility under laboratory constraints and outline a migration path consistent with a hybrid strategy. The work does not include formal performance or scalability benchmarks; external validity is therefore limited and discussed as a threat. Future work proposes a staged pilot (8–12 heterogeneous VMs) with capacity exercises and production-grade economic assessment to generalize the findings.