Nesta tese é analisada a implementação de Inferência Bayesiana em lógica reconfigurável (FPGAs) utilizando uma abordagem ¨Top Down¨. A partir de uma implementação genérica num CPU, e utilizando a linguagem de programação paralela OpenCL, implementámos as componentes de limitadas pela capacidade de processamento em FPGAs instaladas em aceleradores discretos. Um problema de localização genérico foi implementado numa plataforma de computação heterogénea contendo dois CPUs Intel Xeon E5 e quatro FPGAs Intel Stratix V. O sistema foi optimizado de forma a extrair a sua máxima capacidade de processamento através de um cuidadoso balanceamento de carga entre os CPUs e as FPGAs. Foram ainda implementadas várias técnicas de optimização e adquiridas métricas de velocidade, precisão e consumo de energia. Os resultados foram comparados com duas implementações prévias do mesmo problema de localização utilizando Inferência exacta: Uma implementação em ProBT (software comercial para Programação Bayesiana e Inferência) num CPU convencional e uma ¨toolchain¨ genérica desenvolvida sob a alçada do Projecto Europeu FET BAMBI (Bottom-up Approaches to Machines dedicated to Bayesian Inference) utilizando hardware dedicado não-convencional. Foram ainda analisados os impactos do OpenCL na utilização de recursos da FPGA. As várias limitações no suporte oficial a OpenCL dos fabricantes e comercializadores encontradas durante a implmentação foram analizadas. Por último, são propostas oportunidades de trabalho futuro sob este tópico.

A classificação de objetos é um problema com grande relevância em visão por computador, uma vez que pode ser integrada em um enorme conjunto de aplicações alvo, taiscomo agricultura e segurança. No presente, existe um conjunto de soluções que resolvemeste problema, sendo que, as que possuem maior sucesso, dependem de redes neuronais.As mais conhecidas são o GoogleNet, a AlexNet e o YOLO. No entanto, o seu processamento subjacente requer plataformas de alta performance tais como GPUs, clusters deCPUs ou ASICs customizados. Excluindo os ASICs, que tem um elevado custo, massão menos genéricos, elas tipicamente têm um elevado consumo energético e não sãoadequadas a sistemas embebidos. No entanto, tem havido progresso em abordagens debaixo consumo devido em parte ao mercado dos smartphones e tablets, estando disponíveismixes de arquiteturas (CPUs e GPUs) com lógica reconfigurável (FPGAs). Neste trabalho,propomos uma série de implementações de redes neuronais quantizadas em plataformashíbridas, explorando completamente o espaço de design, a performance de classificaçãoe a eficiência energética. O algoritmo subjacente é analisado, e os componentes chavepara computação concorrente e paralela identificados. O mapeamento na plataforma foiexplorado, desde a implementação CPU base até uma completamente customizada quemaximiza o uso dos recursos disponíveis. Um conjunto de métricas é considerado para aavaliação das diferentes configurações. No final, conseguimos classificadores de objetoscom diferentes caracteristicas a correr em dois dispositivos de baixo consumo. As análisesrealizadas às implementações suportaram a fiabilidade da compressão de redes neuronaisde convolução para caber nos dispostivos alvo, através da redução da precisão dos seusparâmetros.

High-Performance Computing involves exploiting the capabilities of powerful computing resources to achieve high computational performance, efficiency, and scalability. By enabling to process complex tasks and/or large amounts of data efficiently, HPC plays an essential role in multiple domains. Parallelization and distribution of workloads across multiple processing resources is at the core of HPC and has been done via many approaches, including different programmatic models and service frameworks. In recent years, HPC has been coupled with Containerization, as a way to deploy, manage and run workloads in an automated and efficient manner, including those relying on accelerators. The performance of heterogeneous workloads, however, depends on the behavior of the platform scheduler, and of the mechanisms used to share accelerators, being also constraint by the limited number of accelerators that each node may host. This paper describes an approach by which the last limitation may be overcome, using a Kubernetes cluster as a show case. The approach builds on the integration of Kubernetes with rOpenCL, an OpenCL API forwarder for remote execution of OpenCL calls. This combination may also be particularly useful in Edge Computing scenarios, where containerized edge services gain the ability to access, transparently and efficiently, remote (e.g. cloud-based) accelerators. Some preliminary experimental results are presented, demonstrating the feasibility of this integration, and the impact on performance for an OpenCL application.

In the last few years, the computing systems processing capabilities have increased significantly, changing from single-core to multi-core and even many-core systems. Accompanying this evolution, local networks have also become faster, with multi-gigabit technologies like Infiniband, Myrinet and 10G Ethernet. Parallel/distributed programming tools and standards, like POSIX Threads, OpenMP and MPI, have helped to explore these technologies and have been frequently combined, giving rise to Hybrid Programming Models. Recently, co-processors like GPUs and FPGAs, started to be used as accelerators, requiring specialized frameworks (like CUDA for NVIDIA GPUs). Presented with so much heterogeneity, the industry formulated the OpenCL specification, as a standard to explore heterogeneous systems. However, in the context of cluster computing, one problem surfaces: OpenCL only enables a developer to use the devices that are present in the local machine. With many processor devices scattered across cluster nodes (CPUs, GPUs and other co-processors), it then became important to enable software developers to take full advantage of the full cluster device set. This dissertation demonstrates and evaluates an OpenCL extension, named clOpenCL, which supports the simple deployment and efficient running of OpenCL-based parallel applications that may span several cluster nodes, thus expanding the original single-node OpenCL model. The main contributions are that clOpenCL i) offers a transparent approach to the porting of traditional OpenCL applications to cluster environments and ii) provides significant performance increases over classical (non-)hybrid parallel approaches. Nos últimos anos, a capacidade de processamento dos sistemas de computação aumentou significativamente, passando de CPUs com um núcleo para CPUs multi-núcleo. Acompanhando esta evolução, as redes locais também se tornaram mais rápidas, com tecnologias multi-gigabit como a Infiniband, Myrinet e 10G Ethernet. Ferramentas e standards paralelos/distribuídos, como POSIX Threads, OpenMP e MPI, ajudaram a explorar esses sistemas, e têm sido frequentemente combinados dando origem a Modelos de Programação Híbrida. Mais recentemente, co-processadores como GPUs e FPGAs, começaram a ser utilizados como aceleradores, exigindo frameworks especializadas (como o CUDA para GPUs NVIDIA). Deparada com tanta heterogeneidade, a indústria formulou a especificação OpenCL, como sendo um standard para exploração de sistemas heterogéneos. No entanto, no contexto da computação em cluster, um problema surge: o OpenCL só permite ao desenvolvedor utilizar dispositivos presentes na máquina local. Com tantos dispositivos de processamento espalhados pelos nós de um cluster (CPUs, GPUs e outros co-processadores), tornou-se assim importante habilitar os desenvolvedores de software, a tirarem o máximo proveito do conjunto total de dispositivos do cluster. Esta dissertação demonstra e avalia uma extensão OpenCL, chamada clOpenCL, que suporta a implementação simples e execução eficiente de aplicações paralelas baseadas em OpenCL que podem estender-se por vários nós do cluster, expandindo assim o modelo original de um único nó do OpenCL. As principais contribuições referem-se a que o clOpenCL i) oferece uma abordagem transparente à portabilidade de aplicações OpenCL tradicionais para ambientes cluster e ii) proporciona aumentos significativos de desempenho sobre abordagens paralelas clássicas (não) híbridas.

Nowadays, most computers are equipped with Graphics Processing Units (GPUs) to provide massive-scale parallelism at a low cost. Parallel programming is necessary to exploit this architectural capacity fully. However, it represents a challenge for programmers since it requires refactoring algorithms, designing parallelism techniques, and hardwarespecific knowledge. Moreover, GPU parallelism is even more challenging since GPUs have peculiar hardware characteristics and employ a parallelism paradigm called many-core programming. In this sense, parallel computing research has focused on studying efficient programming techniques for GPUs and developing abstractions that reduce the effort when writing parallel code. SPar is a domain-specific language (DSL) that goes in this direction. Programmers can use SPar to express stream parallelism in a simpler way without significantly impacting performance. SPar offers high-level abstractions via code annotations while the SPar compiler generates parallel code. SPar recently received an extension to allow parallel code generation for CPUs and GPUs in stream applications. The CPU cores control the flow of data in the generated code. At the same time, the GPU applies massive parallelism in the computation of each stream element. To this end, SPar generates code for an intermediate library called GSParLib, a pattern-oriented parallel API that provides a unified programming model targeting CUDA and OpenCL runtime, allowing parallelism exploitation of different vendor GPUs. However, the GPU support for both SPar and GSParLib is still in its initial steps; they provide only basic features, and no studies have comprehensively evaluated SPar and GSParLib?s performance. This work contributes by parallelizing representative high-performance computing (HPC) benchmarks, implementing new features and optimizations for GPUs in the GSParLib and SPar, and presenting a method for providing agnostic frameworks independent of low-level programming interfaces. Our set of improvements covers most of the critical limitations of GSParLib regarding performance and programmability. In our experiments, the optimized version of GSParLib achieved up to 54,500.00% of speedup improvement over the original version of GSParLib on data parallelism benchmarks and up to 718,43% of throughput improvement on stream parallelism benchmarks.

Most computers nowadays are heterogeneous, composed of a Central Processing Unit (CPU) and one or more Graphics Processing Units (GPUs). In order to harness the power of each of these devices, developers must have experience with low-level toolchains such as CUDA, and expert knowledge of the underlying architecture. However these low-level approaches add several layers of complexity to the task at hand. High-level programming models such as the Marrow framework are used to attenuate the arduous task that is offloading computation to accelerator devices. Usually, they do so by abstracting memory management and implicitly parallelizing workloads by exposing high-level constructs to the programmer. However, these frameworks come with several limitations and it isn’t always possible to maximize performance as this might require writing specific code to map computation to a device. In this thesis we ported several programs implemented in other frameworks and plat- forms to the Marrow framework, which allowed us to better understand its limitations and further extend and optimize the framework. An iterative process was used, where we started by analyzing how a given program was implemented on a given framework, secondly we investigated if the program could be implemented in Marrow’s current state. If not, we extended Marrow by improving its features, in order to make the implementa- tion possible. Then we implemented and benchmarked the given program, and used the performance comparisons as a tool to further optimize the framework. With the development of this thesis we managed to implement several applications with the Marrow framework, which allowed us to add several new features such as the inclusive scan, matrix multiplication operation, the zip and unzip functions, and we significantly improved the flexibility of Marrow’s constructs such as that of Marrow’s exclusive scan. Furthermore, we managed to better understand Marrow’s performance bottlenecks through the Marrow profiler, and optimize asynchronous memory transfers.

Most computers nowadays are heterogeneous, composed of a Central Processing Unit (CPU) and one or more Graphics Processing Units (GPUs). In order to harness the power of each of these devices, developers must have experience with low-level toolchains such as CUDA, and expert knowledge of the underlying architecture. However these low-level approaches add several layers of complexity to the task at hand. High-level programming models such as the Marrow framework are used to attenuate the arduous task that is offloading computation to accelerator devices. Usually, they do so by abstracting memory management and implicitly parallelizing workloads by exposing high-level constructs to the programmer. However, these frameworks come with several limitations and it isn’t always possible to maximize performance as this might require writing specific code to map computation to a device. In this thesis we ported several programs implemented in other frameworks and plat- forms to the Marrow framework, which allowed us to better understand its limitations and further extend and optimize the framework. An iterative process was used, where we started by analyzing how a given program was implemented on a given framework, secondly we investigated if the program could be implemented in Marrow’s current state. If not, we extended Marrow by improving its features, in order to make the implementa- tion possible. Then we implemented and benchmarked the given program, and used the performance comparisons as a tool to further optimize the framework. With the development of this thesis we managed to implement several applications with the Marrow framework, which allowed us to add several new features such as the inclusive scan, matrix multiplication operation, the zip and unzip functions, and we significantly improved the flexibility of Marrow’s constructs such as that of Marrow’s exclusive scan. Furthermore, we managed to better understand Marrow’s performance bottlenecks through the Marrow profiler, and optimize asynchronous memory transfers.