devices and applications in recent years can be attributed partly to the emergence of several new IoT startup companies and potential applications. While many of these startups offer significant innovations in the IoT, some of them lack security expertise, resulting in the development of ill-equipped IoT devices and applications in terms of security. For example, one of the fundamental problems faced by non-security experts in the IoT space is how to select the right Lightweight Cryptographic Algorithm (LWCA) for a given security requirement. To address this specific problem, an IoT Hardware Platform Security Advisor (IoT-HarPSecA) framework is proposed in this paper. The security framework is aimed at facilitating the choice of specific security algorithms given a set of security goals, hardware specifications, message payload size, application area, and energy requirement. Within the scope of this framework, we develop an easy-to-use tool in C++ that allows users to interact with the IoT-HarPSecA framework. The tool can potentially help non-security experts, such as electronics and computer engineers as well as application developers make informed decisions on selecting the appropriate security algorithms for their various applications. Finally, the paper presents some preliminary results and discussion.

A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal, 0.35 μm CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.

Opportunistic radio (OR) systems usually identify and exploit unused spectrum resources in the frequency domain. Targeting opportunities in the time domain of course yields more stringent timing requirements for the opportunistic system, but enables a more optimized resource usage when spectrum opportunities are limited, like for unlicensed bands. This paper describes a hardware demonstrator of such an OR system detecting and using temporal opportunities, and particularly focuses on the key modules required to achieve the opportunistic functionality. To this end, it presents an exclusive implementation of a cyclostationarity sensing algorithm, and proposes a low complexity decision-making algorithm, which performs real-time regulation of the OR communications. Finally, it includes collaborative sensing features to address efficiently the hiddennode scenario. The demonstrator operates in the 2.4 GHz band, and has been validated by sharing the spectrum resource with a standard IEEE 802.11g primary system (PS) running a video streaming application, without perceptible impact of the OR system. It should finally be emphasized that the concepts and techniques undertaken can easily be transposed to any packet based transmission over OFDM or W-CDMA PHY.

This thesis aims to investigate low-complexity digital signal processing techniques for coherent optical transmission systems targeting an efficient hardware implementation, in terms of chip area and power consumption. Novel and reduced complexity equalization techniques that compensate impairments such as fiber linear and nonlinear effects and laser phase noise are proposed in conjunction with the numerical assessment, experimental demonstration in offine and in real-time operation. Low-complexity digital equalization technique for chromatic dispersion (CD) based on a distributive architecture of time-domain (TD) FIR filter is experimentally assessed in a 100 Gb/s and 400 Gb/s transmission system. This technique is compared against the standard time- and frequency-domain CD equalizer revealing a significant reduction gain in terms implementation complexity, which is quantified in terms of number of real multiplications, real additions and processing latency. Additionally, the real-time operation of the proposed technique is demonstrated. Hardware efficient digital backpropagation (DBP) based on timedomain implementation of split-step Fourier method is proposed based on step-size randomization and partitioned quantization techniques to reduce the requirements of hardware implementation.The proposed technique is experimentally demonstrated over long-haul transmission, enabling penalty-free operation with very low number of bits for FIR filter coefficients when compared to the standard techniques. An increased maximum reach is achieved when compared with standalone chromatic dispersion equalization. Finally, a comprehensive study of the phase noise effect in a coherent optical transmission system is performed. A two-stage carrier phase estimation algorithm is explored and optimized to provide an efficient hardware implementation. The trade-off between performance and complexity is numerically assessed and the hardware implementation is conducted targeting an FPGA platform. The results indicate that the optimized algorithm is an attractive solution for an efficient hardware implementation of carrier phase recovery.

Neste trabalho apresenta-se uma proposta de uma técnica para implementação em hardware, das estruturas básicas de uma Rede Neural Competitiva, baseada em técnicas analógicas. Através desta proposta, será abordada uma das classes mais interessantes de Redes Neurais Artificiais (RNA) que são as Redes Neurais Competitivas (RNC), que possuem forte inspiração biológica. As equações fundamentais que descrevem o comportamento da RNC foram derivadas de estudos interdisciplinares, a maioria envolvendo observações neurofisiológicas. O estudo do neurônio biológico, por exemplo, nos leva a clássica equação da membrana. A técnica mostrada para a implementação das Redes Neurais Competitivas se baseia no use das técnicas analógicas. Estas conduzem a um projeto mais compacto além de permitirem um processamento em tempo real, visto que o circuito computacional analógico altera simultaneamente e continuamente todos os estados dos neurônios que se encontram interligados em paralelo. Para esta proposta de implementação, a mostrado que as equações fundamentais que governam as Redes Neurais Competitivas possuem uma relação com componentes eletrônicos básicos, podendo então, serem implementados através destes simples componentes com os quais as equações fundamentais se relacionam. Para tanto, é mostrado por meio de simulações em software, o comportamento das equações fundamentais deste tipo de Redes Neurais, e então, é comparado este comportamento, com os obtidos através de simulações elétricas dos circuitos equivalentes oriundos destas equações fundamentais. Mostra-se também, em ambas as simulações, uma das características mais importantes existentes nos modelos de RNC, conhecida como Memória de Tempo Curto (STM). Por fim, é apresentada uma aplicação típica na área de clusterização de padrões utilizando pesos sinápticos, a fim de demonstrar a implementação utilizando as técnicas descritas durante o trabalho. Esta aplicação é demonstrada através de simulações elétricas, sendo estas realizadas para tipos diferentes de tecnologia, mostrando assim, o correto desempenho da proposta deste trabalho.